1. Field of the Invention
The present invention relates to a dynamic random access memory (referred to as a DRAM hereinafter) and more particularly, to a CMOS (Complementary Metal Oxide Semiconductor) DRAM using a system of precharging a bit line to be (1/2)V.sub.CC.
2. Description of the Prior Art
FIG. 1 is a diagram showing a structure of a conventional CMOS.multidot.DRAM, and FIG. 2 is a schematic circuit diagram showing a main portion of FIG. 1.
Referring to FIG. 1, a plurality of word lines WLl to WLm and a plurality of pairs of bit lines BLl and BLl to BLn and BLn are arranged to intersect with each other, memory cells M being provided at intersections thereof.
The word lines WLl to WLm are connected to a row decoder 5. The row decoder 5 is responsive to an applied row address signal for applying a selecting signal at a high level to any of the word lines WLl to WLm. The bit line pairs BLl and BLl to BLn and BLn are connected to input/output lines I/O and I/O through MOSFETs Q8 and Q9, respectively. Each of the transistors Q8 and Q9 has a gate connected to a column decoder 6. The column decoder 6 is responsive to an applied column address signal for applying column address selecting signals Yl to Yn to the gates of the corresponding transistors Q8 and Q9. An N channel sense amplifier 1, a P channel sense amplifier 2, an equalizing circuit 3 and a precharge potential holding circuit 4 are connected to each of the bit line pairs BLl and BLl to BLn and BLn.
FIG. 2 is a schematic circuit diagram showing a portion of one of the bit line pairs BL and BL, which is disclosed in Digest of Technical Papers pp. 252-253 in International Solid-State Circuits Conference, 1985 (ISSCC '85).
Referring to FIG. 2, an N channel sense amplifier 1 comprises N channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) Q1 and Q2. A P channel sense amplifier 2 comprises P channel MOSFETs Q3 and Q4. Each of the FETs Q1 and Q3 has a drain connected to a bit line BLj, and each of the FET Q2 and Q4 has a drain connected to a bit line BLj. Each of the FETs Q1 and Q3 has a gate connected to a bit line BLj, and each of the FETs Q2 and Q4 has a gate connected to a bit line BLj. Each of the FETs Q1 and Q2 has a source connected to a grounding conductor of a potential V.sub.SS through a line L.sub.N and a sense amplifier driving N channel MOSFET Q.sub.SN. The FET Q.sub.SN has a gate receiving a sense amplifier triggering signal S.sub.N. The line L.sub.N transmits a sense amplifier driving signal .phi..sub.N. Each of the FETs Q3 and Q4 has a source connected to a power supply line V.sub.P of the potential V.sub.CC through a line L.sub.P and a sense amplifier driving P channel MOSFET Q.sub.SP. The FET Q.sub.SP has a gate receiving a sense amplifier triggering signal S.sub.P. The line L.sub.P transmits a sense amplifier driving signal .phi..sub.P.
A memory cell M comprises an FET Q.sub.S and a capacitor C.sub.S. The capacitor C.sub.S is connected to the bit line BLj through the FET Q.sub.S. The FET Q.sub.S has a gate connected to a word line WLi.
An equalizing circuit 3 comprises an FET Q5 connected between the bit line BLj and the bit line BLj. The FET Q5 has a gate connected to a line L.sub.Q for applying an equalize signal EQ.
A precharge potential holding circuit 4 comprises FETs Q6 and Q7 connected in series between the bit lines BLj and BLj. A line L.sub.BL for applying a bit line precharging potential V.sub.BL is connected to a node of the FETs Q6 and Q7. The bit line precharging potential is generally selected to be an intermediate potential between the power supply potential V.sub.CC and the ground potential V.sub.SS, i.e., (1/2)V.sub.CC.
Furthermore, the bit lines BLj and BLj are connected to input/output lines I/O and I/O through transferring FETs Q8 and Q9, respectively. Each of the FETs Q8 and Q9 has a gate receiving a column address selecting signal Yj.
Referring now to FIG. 2 and FIG. 3 of a waveform diagram for explaining operation, description is made on operation of the above described DRAM. It is assumed that the content stored in the capacitor C.sub.S is "1".
In FIG. 3, when an external RAS signal (Ext.RAS) falls, the DRAM is rendered active, so that an external row address signal is latched in a chip. Then, the equalize signal EQ attains a low level. Therefore, equalizing of the bit lines BL and BL is stopped and the line L.sub.BL receiving the bit line precharging potential V.sub.BL and the bit lines BL and BL are disconnected.
Then, the potential on a word line selected in response to the row address signal latched in the chip attains a high level. It is assumed that the word line WLi shown in FIG. 2 is selected. When the potential on the word line WLi attains a high level, the FET Q.sub.S is turned on, so that charges stored in the capacitor C.sub.S are transferred to the bit line BLj. As a result, the potential on the bit line BLj is higher than the potential on the bit line at the time of equalizing, that is, the bit line precharging potential V.sub.BL. Then, when the sense amplifier triggering signal S.sub.N attains a high level and the sense amplifier triggering signal S.sub.P attains a low level, the FETs Q.sub.SN and Q.sub.SP are turned on. As a result, the sense amplifier driving signal .phi..sub.N attains a low level and the sense amplifier driving signal .phi..sub.P attains a high level. Therefore, the N channel sense amplifier (the first sense amplifier) 1 and the P channel sense amplifier (the second sense amplifier) 2 operate, so that the potential difference between the bit lines BLj and BLj is amplified. As a result, the content "1" stored in the capacitor C.sub.S is read out to the bit line BLj.
Then, the column address selecting signal attains a high level. When the bit lines BLj and BLj are selected, the column address signal Yj attains a high level, so that data on the bit lines BLj and BLj are transferred to the input/output lines I/O and I/O through the transferring FETs Q8 and Q9, respectively.
Then, the DRAM is rendered inactive in response to the rise of the external RAS signal. The external RAS signal attains a high level and then, the potential on the selected word line WLi attains a low level, so that the FET Q.sub.S is turned off. Then, the sense amplifier triggering signal S.sub.N attains a low level and the sense amplifier triggering signal S.sub.P attains a high level. Then, the equalize signal EQ attains a high level. As a result, the bit lines BLj and BLj are equalized, so that the potentials thereon become (1/2)V.sub.CC. At the same time, the line L.sub.BL receiving the precharge potential V.sub.BL is connected to the bit lines BLj and BLj, so that the potentials on the bit lines BLj and BLj are held at (1/2)V.sub.CC. At that time, the sense amplifier driving signal .phi..sub.N is changed from a low level to an intermediate level, and the sense amplifier driving signal .phi..sub.P is changed from a high level to an intermediate level.
As described in the foregoing, in the CMOS dynamic sense amplifier included in the conventional DRAM, the bit lines are connected to the line L.sub.BL receiving the bit line precharge potential V.sub.BL, so as to prevent the bit line precharging potential from varying due to leak current or the like caused during the inactive state of the DRAM. In addition, according to the above described conventional example, the sense amplifier driving signals .phi..sub.N and .phi..sub.S are held at the bit line precharging potential V.sub.BL. Therefore, the sense amplifier driving signals .phi..sub.N and .phi..sub.S are held at the same potential as those on the bit lines.
However, in a structure of the conventional DRAM shown in FIG. 1, many bit line pairs, sense amplifiers and the like are arranged in a chip of the DRAM. Since the bit line precharging potential V.sub.BL and the sense amplifier driving signals .phi..sub.N and .phi..sub.P are shared with many bit line pairs and the sense amplifiers, the interconnection lengths for the bit line precharging potential V.sub.BL and the sense amplifier driving signals .phi..sub.N and .phi..sub.P are increased. Thus, as described above, if and when the bit lines BLj and BLj and the lines L.sub.N and L.sub.P for transmitting the sense amplifier driving signals .phi..sub.N and .phi..sub.P are connected to the line L.sub.BL for applying the precharge potential V.sub.BL, outside a portion having many bit line pairs, sense amplifiers and the like arranged (referred to as an array portion hereinafter), the line L.sub.BL and the lines L.sub.N and L.sub.P intersect with the other many interconnections. As a result, the lines L.sub.BL, L.sub.N and L.sub.P are liable to be affected by noise due to capacitive coupling between the lines and the interconnections. More particularly, as shown in FIG. 1, when the line L.sub.BL and the lines L.sub.N and L.sub.P are arranged spaced apart from each other, the interconnections are affected by noises having different phases more increasingly.
Furthermore, if and when the potential of the N channel sense amplifier driving signal .phi..sub.N is decreased due to such noise, as compared with the potential which is lower, by a threshold voltage of the N channel FET, than the precharge potential on the bit line, or is increased due to such noise, as compared with the potential which is higher, by the absolute value of a threshold voltage of the P channel FET, than the precharge potential on the bit line, the activation of the sense amplifiers is unnecessarily hastened, and the sensitivity of the sense amplifiers is liable to be deteriorated due to variation in characteristics of transistors constituting each of the sense amplifiers, which is described in, for example, National Telecommunication Conference, 1982, Lecture Number 439.
A method for solving a part of the problems is disclosed in, for example, Japanese Patent Publication No. 11393/1985, which is shown in FIG. 4.
FIG. 4 illustrates a sense amplifier portion comprising only N channel transistors. In addition to FETs Q41 and Q42 constituting the sense amplifier, FETs Q43 and Q44 are connected between the bit lines BL and BL and a line L.sub.N for applying a sense amplifier driving signal .phi..sub.N. Each of the FETs Q43 and Q44 has a gate receiving a sense amplifier pull-up signal .phi..sub.1. The line L.sub.N is connected to potentials V.sub.1 and V.sub.2 through sense amplifier activating FETs Q47 and Q48. The FETs Q47 and Q48 have gates receiving sense amplifier triggering signals S.sub.N1 and S.sub.N2, respectively. The bit lines BL and BL are connected to a power supply potential V.sub.CC through precharging FETs Q45 and Q46, respectively.
Since the above described FETs Q43 and Q44 cause the bit lines BL and BL and the sense amplifier driving signal .phi..sub.N to be the same potential in the vicinity of the sense amplifier while the DRAM is rendered inactive, the above described problem of activating the sense amplifier too early is avoided.
As shown in FIG. 4, if and when the sense amplifier portion comprises only the N channel transistors, the bit lines are precharged to be the power supply potential V.sub.CC. Since the precharging FETs Q45 and Q46 are generally provided for each sense amplifier, an interconnection for applying the power supply potential V.sub.CC is necessarily arranged in the array portion. In the case of a CMOS sense amplifier, since an interconnection for applying a bit line precharging potential V.sub.BL must be arranged in the array portion by some method, there occurs the above described problem due to noise.
Furthermore, Japanese Patent Laying-Open Gazette No. 82279/1982 discloses a semiconductor memory device in which a precharge potential V.sub.CC is applied to bit line pairs through a line for applying a driving signal to an N channel sense amplifier. In the semiconductor memory device, the line for applying the sense amplifier driving signal is connected to the power supply potential V.sub.CC through an N channel MOSFET. However, in the semiconductor memory device, since the sense amplifier is of an N channel type and the precharge potential is V.sub.CC, the potential which is higher, by at least a threshold voltage V.sub.TH of the N channel MOSFET, than the power supply potential V.sub.CC must be applied to a gate of the N channel MOSFET connected between the power supply potential V.sub.CC and the above described line. In addition, since the potential on the bit line pair which became a potential (1/2)V.sub.CC by short-circuiting the bit line pair must be increased to the power supply potential V.sub.CC, the semiconductor memory device consumes much power.